module portOut (
    input wire clk,
    input wire rst,
    input wire dequeue_en_queue,
    input wire [15:0] dequeue_value,
    input wire date_en_group,
    input wire [31:0] data_in_group,
    input wire data_en_special,
    input wire [31:0] data_in_special,
    output reg port_idle,
    output reg sop,
    output reg eop,
    output reg vld,
    output reg [31:0] port_data_out
);
    reg [1:0] work_state;
    reg [15:0] history_dequeue_value;
    reg [31:0] memory [0:511];
    integer i;
    integer file_descriptor;  // 文件描述符
    integer num = 1;// 文件名
    reg save_en;

    always @(posedge clk) begin
        if (rst) begin
            sop <= 0;
            eop <= 0;
            port_idle <= 1;
            vld <= 0;
            port_data_out <= 0;
            history_dequeue_value <= 0;
            work_state <= 2'b00;
            i <= 0;
            save_en <= 0;
        end
        else begin
            case (work_state)
                2'b00: begin
                    if (dequeue_en_queue) begin
                        history_dequeue_value <= dequeue_value;
                        work_state <= 2'b10;
                    end
                end
                2'b10: begin
                    if (data_en_special==1 && history_dequeue_value[15:10]<16) begin
                        work_state <= 2'b11;
                        port_idle <= 0;
                        sop <= 1;
                        vld <= 1;
                        port_data_out <= data_in_special;
                        memory[i] <= data_in_special;
                        i <= i + 1;
                    end

                    if (date_en_group==1 && history_dequeue_value[15:10]>15) begin
                        work_state <= 2'b01;
                        port_idle <= 0;
                        sop <= 1;
                        vld <= 1;
                        port_data_out <= data_in_group;
                        memory[i] <= data_in_group;
                        i <= i + 1;
                    end
                end
                2'b11: begin
                    if (data_en_special == 0) begin
                        vld <= 0;
                        port_idle <= 1;
                        port_data_out <= 0;
                        if (vld == 1) begin
                            eop <= 1;
                        end
                        work_state <= 2'b00;
                    end
                    else begin
                        port_data_out <= data_in_special;
                        vld <= 1;
                    end
                end
                2'b01: begin
                    if (date_en_group == 0) begin
                        vld <= 0;
                        port_idle <= 1;
                        port_data_out <= 0;
                        if (vld == 1) begin
                            eop <= 1;
                        end
                        work_state <= 2'b00;
                    end
                    else begin
                        port_data_out <= data_in_group;
                        vld <= 1;
                    end
                end
                default: begin
                    work_state <= 2'b00;
                end
            endcase

            if (sop == 1) begin
                sop <= 0;
            end

            if (eop == 1) begin
                eop <= 0;
            end
        end
    end
endmodule